1. Field of the Invention
The present invention generally relates to the data transmission field. More particularly, the present invention relates to a method and a device for demapping a tributary from a higher order synchronous frame to a lower order synchronous frame recovering lower order synchronism. Furthermore, the present invention relates to a network node comprising such a device.
2. Description of the Prior Art
In a synchronous transmission network, data are transported as tributary signals (or simply “tributaries”) by synchronous frames, which are synchronized by a network reference clock.
Synchronous frames are typically arranged in a synchronous hierarchy. A tributary may be transported by frames of different layers of the synchronous hierarchy.
An asynchronous or plesiochronous tributary which is transported by a synchronous frame of a certain layer, before reception, is typically demapped (i.e. extracted) from the frame. Such a demapping is typically performed by a device which is termed “demapper” (or “desynchronizer”).
A special application of a demapper is demapping a tributary from a frame of a certain hierarchy layer into a frame of a lower hierarchy layer, i.e. the tributary is extracted from a frame of a certain hierarchy layer and it is inserted into a frame of a lower hierarchy layer.
In the following description, for simplicity, reference will be made to an exemplary two-layer synchronous hierarchy: frames of the lower layer will be termed “lower order frames”, while frames of the higher layer will be termed “higher order frames”. Nevertheless, the present invention is applicable to any synchronous hierarchy, comprising any number of layers (e.g. Sonet, SDH, etc.)
A synchronous frame (either an higher order synchronous frame or a lower order synchronous frame) may comprise, in addition to the tributary, redundancy bits. Typically, such redundancy bits are used to implement error correction techniques, such as the FEC (“Forward Error Correction”) technique. Number and positions of the redundancy bits in a frame are generally standardized. Further, number and positions of the redundancy bits are typically different in higher order frames and in lower order frames of a same synchronous hierarchy.
When a tributary is demapped from a higher order frame into a lower order frame, possible redundancy bits of the higher order frame are removed, and only tributary words are inserted into the lower order frame. After mapping, new redundancy bits are calculated and inserted into the lower order frame.
A synchronous frame typically comprises a frame alignment word. Frame alignment words of successive frames are typically placed at a same predefined position of the frames (i.e. frame alignment words of successive frames are spaced by a frame period). For instance, a higher order frame typically comprises, at a predefined position, a higher order frame alignment word. Besides, such a higher order frame comprise tributary and redundancy bits, wherein the tributary further comprises a lower order frame alignment word. Such a lower order frame alignment word is positioned in any position of the higher order frame.
When a tributary is demapped from a higher order frame to a lower order frame, the demapper, for properly operating, has to be capable of inserting the tributary in lower order frames so that the lower order frame alignment words of successive lower order frames are placed at a predefined position of the lower order frames. In other words, a demapper has to properly recover the lower order synchronism.
In the following description, for simplicity, the lower order frame alignment word will be briefly termed “alignment word”.
Typically, a demapper receiving a higher order frame writes the tributary words (including the alignment word) in a memory, at a certain writing rate. Then, the tributary words (including the alignment word) are read from the memory at a certain reading rate.
For identifying the alignment word, in a know demapper, it is known to mark each tributary word written into the memory through a respective alignment bit. For instance, such an alignment bit may be 1 for the alignment word, and 0 for the remaining tributary words. Therefore, while reading, the alignment bit allows to recognize the alignment word, so that it can be inserted at a predefined position of the lower order frame.
In a known demapper, the writing address of each tributary word is given by a writing counter, which is incremented each time a tributary word is written into the memory. Similarly, in such a known demapper, the reading address of each tributary word is given by a reading counter, which is incremented each time a tributary word is read from the memory. Therefore, the writing counter is kept fixed while extracting redundancy bits from the higher order frame, while the reading counter is kept fixed while inserting redundancy bits into the lower order frame.
Italian patent application MI2005A001286, filed on Jul. 8, 2005, disclosed a demapper comprising a master writing counter and a master reading counter. The master writing counter is increased by a first value at each clock cycle of higher order frame, while the master reading counter is increased by a second value at each clock cycle of lower order frame. The phase error for estimating justification is calculated according to the master writing counter and the master reading counter. Furthermore, according to MI2005A001286, the demapper comprises a slave writing counter and a slave reading counter. The slave writing counter is synchronized to the master writing counter at a predetermined writing synchronization clock cycle, and it is increased at each clock cycle of the higher order frame wherein a tributary word is written into the memory. Similarly, the slave reading counter is synchronized to the master reading counter at a predetermined reading synchronization clock cycle, and it is increased at each clock cycle of the lower order frame wherein a tributary word is read from the memory. According to MI2005A001286, writing and reading operations are managed according to the slave writing counter and to the slave reading counter, respectively.